ICS854S054I multiplexer equivalent, 4:1 differential-to-lvds clock multiplexer.
* High speed 4:1 differential multiplexer
* One differential LVDS output pair
* Four selectable differential PCLK, nPCLK input pairs
* PCLKx, nPCLKx pairs.
Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental.
The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz. The ICS854S054I has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential arch.
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